For assuring of normal operation of a computer system, a newly manufactured chip that is coupled to both a high-speed bus and a low-speed bus has to be tested to see whether it can successfully receive and transmit signals via those buses. Conventionally, the chip is coupled to an external tester with a high-speed bus end and a low-speed bus end for inputting a test signal from the tester and outputting a response signal to the tester, respectively. The response signal is analyzed to verify the chip.
FIG. 1 illustrates a conventional chip coupled to both a high-speed bus and a low-speed bus and a test method of such a chip. Typically, the chip 10 is coupled to a high-speed bus 12 by one end and coupled to a low-speed bus 14 by another end. The high-speed bus 12, for example, can be a host bus while the low-speed bus 14 can be a PCI bus or a PCI express bus. The chip 10 includes a high-speed bus controller 101 coupled to the high-speed bus 12 for controlling data transmission via the high-speed bus 12, and a low-speed bus controller 102 coupled to the low-speed bus 14 for controlling data transmission via the low-speed bus 14. The chip 10 further includes an upstream control unit 103 disposed between the high-speed bus controller 101 and the low-speed bus controller 102 for transmitting data upwards to the high-speed bus controller 101, and a downstream control unit 104 also disposed between the high-speed bus controller 101 and the low-speed bus controller 102 for transmitting data downwards to the low-speed bus controller 102.
When a test procedure starts, the high-speed controller 101 of the chip 10 receives a test signal issued by an external tester (not shown) via the high-speed bus 12. The test signal is transmitted inside the chip 10 through the high-speed bus controller 101, the downstream control unit 104 and the low-speed bus controller 102 in sequence to be respectively operated or processed. The operated or processed result is then outputted to the tester via the low-speed bus 14 as a response signal. Then the tester may determine whether the chip 10 works normally according to the response signal.
Generally, the high-speed bus that the above chip works with is operated at an extremely high rate up to 6.4 GHz, e.g. a hyper transport bus. Therefore, for testing the chip by inputting the test signal from the high-speed bus end, a matching high-speed tester, which is also costly, is needed. Moreover, with further advance of bus rates, the tester needs to be upgraded or replaced, which is quite cost-ineffective.
In addition, most of the elements in the chip, except the high-speed bus controller 101, are operated at a relatively low speed. When the tester generates a high-frequency signal to run in the low-speed elements, distortion may happen. Particularly, the rate difference between a high-speed bus and a low-speed bus is increasing day by day. For example, the rate of the hyper transport bus is up to 6.4 GHz while the rate of a PCI bus is only 66 MHz. Thus distortion problem becomes more serious.